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This paper presents the design and simulation of a circuit consisting of multiple interacting configurable logic blocks (CLBs) using quantum-dot cellular automata (QCA). Previous work on QCA-based field-programmable gate arrays (FPGAs) has focused on fixed logic and programmable interconnect. In contrast, this work uses CLBs consisting of look-up tables (LUTs). These CLBs have been previously presented in isolation. This paper presents two main contributions. First, we improve the latency and area of the existing CLBs. Second, we simulate four connected CLBs acting as a very simple FPGA. We configure this FPGA to emulate a ripple-carry adder and analyze latency and throughput. We employ a multilevel approach to design specification and simulation. QCA designer software is used for detailed layout and simulation of the individual CLB. For simulations of multiple-CLB circuits, we use the high-level HDLQ Verilog library instead. This hybrid approach provides a high degree of confidence in reasonable simulation time.