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Factorization of large numbers, is of great importance in cryptanalysis, since many security algorithms are based on the fact that factoring of such numbers is an extremely difficult task. The fastest known algorithm for factoring large numbers is the Number Field Sieve (NFS). This algorithm has four main steps. Two of them, the sieving and the linear algebra steps are the more time consuming. In this paper, we introduce and implement a new matrix-by-vector multiplication scheme using a module based run time reconfiguration design, for the linear algebra step. Our implementation is based on Xilinx Virtex FPGA devices with serial 6.5 Gbps transceivers. We compare our system with other proposed architectures and we demonstrate that we can be 19,4 to 57,4 times faster, depending on the parameters of the block Wiedemann algorithm and on the FPGA device used.