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Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design

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4 Author(s)
Smith, A.M. ; Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK ; Constantinides, G.A. ; Wilton, S.J.E. ; Cheung, P.Y.K.

This paper presents a method that combines high-level and low-level architecture parameter exploration. The paper builds on an increasing body of work concerned with modeling reconfigurable architectures, and presents a full area and delay model of an FPGA. The optimization of this model is based on the use of geometric programming, and allows high-level architecture parameter selection and transistor sizing to be done concurrently. We use the framework to demonstrate that concurrent optimization of both high and low-level parameters can lead to significantly different architectural conclusions.

Published in:

Field-Programmable Technology, 2009. FPT 2009. International Conference on

Date of Conference:

9-11 Dec. 2009