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FPGA implementation of a 64-Bit BID-based decimal floating-point adder/subtractor

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3 Author(s)
Amin Farmahini-Farahani ; Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 1415 Engineering Drive, 53706-1691, USA ; Charles Tsen ; Katherine Compton

Demand for decimal floating-point (DFP) arithmetic is growing. Yet most processors do not include hardware DFP support, and must instead use slow software DFP libraries. FPGAs are a potential solution to add hardware-based high-performance, parallel DFP engines to existing compute clusters without completely replacing those systems. This paper describes the FPGA implementation of a 64-bit DFP adder using binary integer decimal (BID) encoding. We present a variety of design tradeoffs possible for different modules of the DFP adder, and compare these for implementation on a Xilinx Virtex-5 FPGA. Choosing the best options, we improve the frequency of the DFP adder from the baseline hardware design's 68 MHz to over 163 MHz and decrease total latency by up to 2.4×. The optimized design requires only a small increase in resources. This is the first presentation of a BID-based DFP adder for FPGAs.

Published in:

Field-Programmable Technology, 2009. FPT 2009. International Conference on

Date of Conference:

9-11 Dec. 2009