By Topic

FPGA implementation of an invasive computing architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Amouri, A. ; Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Nuremberg, Germany ; Arifin, F. ; Hannig, F. ; Teich, J.

Invasive computing is a novel paradigm for exploitation of run-time parallelism of future MPSoC architectures through resource-aware programming and dynamic reconfiguration of the underlying architectures. Based on the state and availability of resources, an invasive algorithm organizes its computation itself. This paper presents a general methodology for mapping invasive algorithms to FPGA-based dynamically reconfigurable architectures. A detailed description of a general invasive architecture on a reconfigurable platform is given. For 1D linear processor architectures, the applicability of this concept is tested and results show substantial flexibility gains with only marginal additional hardware cost.

Published in:

Field-Programmable Technology, 2009. FPT 2009. International Conference on

Date of Conference:

9-11 Dec. 2009