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This work addresses the methods to solve VLSI standard cell placement problem with the objectives of minimizing the wire length and computational time. In this work a parallel GA architecture is designed and the computational time of Genetic algorithm is reduced by means of parallel technique. The proposed algorithms are tested in IBM bench mark circuits. Proposed method is compared with Qplace5.1.67,, Dragon 2.2.3 and Fastplace are found superior in terms of computational time and solution quality.