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Development of a VLSI chip for real time MPEG-2 video decoder

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8 Author(s)
Morimatsu, E. ; Fujitsu Labs. Ltd., Kawasaki, Japan ; Sakai, K. ; Yamashita, K. ; Ohta, M.
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A VLSI chip fully compatible with ISO/IEC 13818 2 (MPEG-2 video) has been developed. The chip is conforming to main profile @ main level of the standard, which realizes real-time decoding of ITU-R Rec.601 format moving pictures. In addition, it is also designed to operate as a part of MPEG-2 encoder. The chip size and power dissipation are minimized by optimizing its architecture and by using hardware macro cells for bulky circuits such as multipliers. As a result, the chip has been implemented with approximately 620K transistors on 11.35×11.35 mm using a triple metal 0.5 μm CMOS technology. The chip has performed well in evaluations on a PC-based testbed

Published in:
Image Processing, 1995. Proceedings., International Conference on  (Volume:3 )

Date of Conference: 23-26 Oct 1995

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