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Novel Low- k Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

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6 Author(s)
Xiaorong Luo ; State key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Yuangang Wang ; Hao Deng ; Jie Fan
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A high-voltage lateral double diffused metal-oxide-semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-k dielectric (LK PSOI) is proposed. The low-k value enhances the electric field strength in the dielectric (EI). The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the EI and BV of LK PSOI with kI = 2 are enhanced by 74% and 19%, respectively.

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Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 2 )