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Browse Journals & Magazines > Electron Devices, IEEE Transa ...> Volume:57 Issue:2 Help

Novel Low- k Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

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6 Author(s)
Xiaorong Luo ; State key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Yuangang Wang ; Hao Deng ; Jie Fan
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A high-voltage lateral double diffused metal-oxide-semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-k dielectric (LK PSOI) is proposed. The low-k value enhances the electric field strength in the dielectric (EI). The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the EI and BV of LK PSOI with kI = 2 are enhanced by 74% and 19%, respectively.

Published in:
Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 2 )

Date of Publication: Feb. 2010

Page(s):
535 - 538
ISSN :
0018-9383
INSPEC Accession Number:
11071264
Digital Object Identifier :
10.1109/TED.2009.2037372
Date of Publication :
08 January 2010
Date of Current Version :
19 January 2010
Issue Date :
Feb. 2010
Sponsored by :
IEEE Electron Devices Society

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