Skip to Main Content
This paper presents a method to implement reconfigurable logic controllers (RLCs) using a new matrix model to describe Petri nets (PNs). The method obtains the general equations and directly translates them into a hardware description language (HDL) to configure a field-programmable gate array (FPGA). To achieve a generalized model in a comprehensible way, several PN examples including timers, counters, and hierarchical subnets are described in detail. The working principles and robustness of the method are validated by simulating each example and by their practical implementation in an RLC.