By Topic

Characterization of NBTI-Induced Interface State and Hole Trapping in SiON Gate Dielectrics of p-MOSFETs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jen-Hao Lee ; Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan ; Anthony S. Oates

We present the analysis of the interface-state generation and hole-trapping components of the VT shift in Si-oxynitride (SiON)-based p-MOSFETs due to the negative bias temperature instability. The amounts of interface-trap creation and hole trapping are separately assessed by three methods in this paper: 1) a separation method that isolates the contribution of interface traps, which assumes that hole trapping saturates very quickly during stress; 2) a novel transconductance (gm) technique which accurately characterizes the interface-trap generation; and 3) measurements of the VT after stress and comparison with a relaxation model using these methods. We find that interface-trap creation is accurately described by reaction-diffusion theory. Meanwhile, holes fill preexisting centers at a low oxide stress field, but trap generation occurs at a higher gate electric field. We suggest that the preexisting hole-trap centers are similar in pure SiO2 and SiON gate dielectrics and determine trapping characteristics at operation conditions.

Published in:

IEEE Transactions on Device and Materials Reliability  (Volume:10 ,  Issue: 2 )