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A new method for improving the performance of network on chip using DAMQ buffer schemes

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2 Author(s)
Jamali, M.A.J. ; CE Dept., Islamic Azad Univ., Shabestar, Iran ; Khademzadeh, A.

Networks on chip (NoCs) are communication infrastructures that offer parallelism and scalability. In this paper we present high performance dynamically allocated multi-queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network. Two virtual channels shared the same buffer space. Fault tolerant mechanisms for interconnection networks are becoming a critical design issue for large massively parallel computers. It is also important to high performance SoCs as the system complexity keeps increasing rapidly. On the message switching layer, we make improvement to boost system performance when there are faults involved in the components communication. The proposed scheme is when a node or a physical channel is deemed as faulty, the previous hop node will terminate the buffer occupancy of messages destined to the failed link. The buffer usage decisions are made at switching layer without interactions with higher abstract layer, thus buffer space will be released to messages destined to other healthy nodes quickly. Therefore, the buffer space will be efficiently used in case fault occurs at some nodes. Simulation results depict that proposed scheme has similar performance using only 62.5% of the buffer size that is used in traditional implementation for NoCs (4% fault rate).

Published in:

Application of Information and Communication Technologies, 2009. AICT 2009. International Conference on

Date of Conference:

14-16 Oct. 2009