By Topic

Estimating power consumption of CMOS circuits modelled as symbolic neural networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Macii, E. ; Dipartimento di Autom. e Inf., Politecnico di Torino, Italy ; Poncino, M.

The authors propose a new approach to the problem of estimating the average power consumption of a CMOS combinational circuit which is based on neural models. Given the gate level description of a circuit, they build the corresponding Hopfield neural network, store it, calculate the energy dissipated by the network and, finally, derive the power dissipated by the original circuit. All the operations above are executed in the symbolic domain, that is algebraic decision diagrams are used to represent and manipulate the graph specification of the neural network modelling the circuit. The approach is viable and computationally efficient. In addition, it produces power estimates which are, on average, as accurate as the ones computed by state-of-the-art power analysis tools

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:143 ,  Issue: 5 )