Referenced Items are not available for this document.
The design and layout of a prototype single precision systolic floating-point processing element (PE) is described. It is intended for use in a class of systolic array processors which perform matrix computations. Each PE is constructed from a digit-serial systolic ring of four programmable cells and performs floating-point multiplication and accumulation. A single PE has been fabricated in a 0.8 μm gallium arsenide E/D MESFET process and has a maximum clock speed of 300 MHz. The chip can be configured into a 16×16 array to achieve a peak computation rate of 2.5 GFLOPS
Published in:
Computers and Digital Techniques, IEE Proceedings -
(Volume:143
,
Issue:
5
)
Date of Publication: Sep 1996
- Page(s):
- 325 - 330
- ISSN :
- 1350-2387
- INSPEC Accession Number:
- 5419803
- Digital Object Identifier :
- 10.1049/ip-cdt:19960635
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Sep 1996
- Sponsored by :
- IET
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