By Topic

Design of a low-latency asynchronous adder using speculative completion

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Nowick, S.M. ; Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

A new general method for designing asynchronous datapath components, called speculative completion, is introduced. The method has many of the advantages of a bundled data approach, such as the use of single-rail synchronous datapaths, but it also allows early completion. As a case study, the method is applied to the high-performance parallel BLC adder design of Brent and Kung (1982). Through careful gate-level analysis, performance improvements of up to 30% over a comparable synchronous implementation are expected

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:143 ,  Issue: 5 )