Cart (Loading....) | Create Account
Close category search window
 

A Power Efficient Baseband Engine for Multiuser Mobile MIMO-OFDMA Communications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jung-Mao Lin ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Hsin-Yi Yu ; Yu-Jen Wu ; Hsi-Pin Ma

In this paper, the authors present a configurable and power efficient multiuser MIMO-OFDMA baseband processor for uplink mobile communications. To solve the carrier frequency offset (CFO) problem in multiuser transmission, an inter-carrier interference-based (ICI-cancellation-based) CFO estimator is implemented based on an iterative search criterion of minimum signal-to-interference-noise (SINR) ratio. Compared to the state-of-the-art methods, the proposed CFO estimator is more robust to transmission configurations (MIMO and multiuser) and CFO variations. Moreover, the authors propose an efficient architecture that saves 78% of the hardware complexity compared to the direct implemented architecture by employing Taylor series expansion for ICI/multiple-access interference (MAI) cancellation. Meanwhile, a 2-D linear channel estimator is also proposed to assist the CFO estimator and track the time-variant multipath channel. Two kinds of MIMO detector, vertical Bell Laboratory layered space-time (V-BLAST) and V-BLAST with maximum likelihood (V-ML), are adopted to minimize output latency and achieve the best ML bit-error-rate (BER) performance. An ASIC fabricated by 0.13 μm 1P8M CMOS technology is measured with 2.31 Mbps/mW power efficiency and less than 1.5 dB implementation loss. In addition, the whole transceiver is integrated and verified by a system-on-chip (SoC) platform to demonstrate its efficacy.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 7 )

Date of Publication:

July 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.