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A low power consumption image acquisition system with the core controller of CPLD, based on LVDS interface and CMOS digital image sensor was designed here. We analyzed the work timing of LVDS interface ship DS90C124 and CMOS digital image sensor MT9V011, designed and simulated the VHDL code of the relevant drive circuit, and did an actual debug operation. The experimental results show that this system has advantages of low-power consumption and high reliability, it can be used in a variety of image processing systems.
Intelligent Information Technology Application, 2009. IITA 2009. Third International Symposium on (Volume:3 )
Date of Conference: 21-22 Nov. 2009