Referenced Items are not available for this document.
A low power consumption image acquisition system with the core controller of CPLD, based on LVDS interface and CMOS digital image sensor was designed here. We analyzed the work timing of LVDS interface ship DS90C124 and CMOS digital image sensor MT9V011, designed and simulated the VHDL code of the relevant drive circuit, and did an actual debug operation. The experimental results show that this system has advantages of low-power consumption and high reliability, it can be used in a variety of image processing systems.
Published in:
Intelligent Information Technology Application, 2009. IITA 2009. Third International Symposium on
(Volume:3
)
Date of Conference: 21-22 Nov. 2009
- Page(s):
- 655 - 657
- Print ISBN:
- 978-0-7695-3859-4
- INSPEC Accession Number:
- 11051820
- Conference Location :
- Nanchang
- Digital Object Identifier :
- 10.1109/IITA.2009.460
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
