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This paper focus on hardware representation and implementation of graph algorithms in reconfigurable hardware (FPGAs) to speeding up the execution. Generally, software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.