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On the application of the Neuron MOS transistor principle for modern VLSI design

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5 Author(s)
W. Weber ; Corp. Res. & Dev., Siemens AG, Munich, Germany ; S. J. Prange ; P. Thewes ; E. Wohlrab
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In this paper, the speed performance, power consumption, and layout area of Neuron MOS transistor circuits are monitored considering the requirements of modern VLSI design. The Neuron MOS transistor is a recently discovered device principle which has a number of input gates that couple capacitively to a floating gate. The floating gate potential controls the current of a transistor channel. This device can be used in logic circuits. A threshold current through the Neuron MOS transistor can be defined that causes a switching of the output of the logic circuits as soon as the channel current surmounts or falls below the specified value. We designed two different multiplier cells, one based on a Neuron MOS inverter, and the other on a Neuron MOS n-MOSFET which is used as one input device of a comparator circuit. Functionality of both cells is proven for data rates up to 50 MHz which represents the first high-speed measurement of a circuit based on this new design principle. A perspective for the upper speed limit found at more than 500 MHz is given by simulation. The new design principle has a layout area reduced by more than a factor of two compared to usual multiplier cells. Moreover, it is shown, that depending on the design chosen, high speed operation leads to considerable power savings. In view of those advantages it is concluded that the principle of threshold logic qualifies for a major breakthrough for packing density improvement of CMOS-based applications

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IEEE Transactions on Electron Devices  (Volume:43 ,  Issue: 10 )