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As telecommunication systems grow in their complexity, research tasks demand quick , yet formal, ways to verify and benchmark. Among the steps to verify and analyze systems prior to the hardware in the loop step, remain the essential part of the research process. The paper presents the issues, results and the experience of using the HPC resources prior to the hardware in the loop verification on the reference designs for FSK and OFDM telecommunication systems, elaborated from the basic models, partitions, ending with the conclusions and implications on the final run time hardware implementation as HIL (hardware in the loop) concept.
Date of Conference: 18-20 June 2009