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Energy recovery circuits using reversible and partially reversible logic

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2 Author(s)
Yibin Ye ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; K. Roy

This paper presents a new family of logic gates for low energy computing using pulsed power CMOS logic. The logic gates use the principles of adiabatic-switching and results show that in typical cases 90% of the energy can be recovered with operating frequency around 1 MHz. Constant capacitance condition is enforced in our designs so that signals' energy can be efficiently recycled in the chip. We also present a detailed analysis and modeling of energy dissipation in adiabatic circuits. The models were experimentally validated using the circuit simulator SPICE. A simplified version of adiabatic logic with simplicity comparable to static CMOS circuits is also presented. For a 2×2 multiplier using this type of logic, 60% of energy can be saved over static CMOS case at 20 MHz and there is 35% less energy consumption at 100 MHz

Published in:

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications  (Volume:43 ,  Issue: 9 )