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Hierarchical test generation under architectural level functional constraints

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2 Author(s)
Jaushin Lee ; Silicon Graphics Inc., Mountain View, CA, USA ; J. H. Patel

In hierarchical test generation, the test vectors for the low level structure of the module under test are computed and then justified at a high level. In the module test computation procedure, a low level ATPG tool is conventionally applied to the complete structure of that particular module without adding extra information. Due to the architectural level functional constraints applied to the inputs of that module, many of the test vectors being computed are not justifiable at the high level. Therefore, high efficiency cannot be achieved without managing the functional constraint problem in the hierarchical ATPG process. In this paper, both top-down and bottom-up approaches are addressed. It is shown that the valid control code abstraction and test cube justification techniques are very effective to overcome the architectural level functional constraint problem and to achieve high efficiency in test computation. The proposed algorithms have been implemented in our hierarchical ATPG package and promising experimental results have been derived. We conclude that architectural level functional constraints can be efficiently avoided through these techniques

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:15 ,  Issue: 9 )