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Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults

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2 Author(s)
Franklin, M. ; Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA ; Saluja, K.K.

State-of-the-art RAM chips are designed with spare rows and columns for reconfiguration purposes. After a RAM chip is reconfigured, physically adjacent spare cells may no longer have consecutive logical addresses. Another aspect that results in distinct logical and physical neighborhoods in RAM's is the scrambling of address lines, necessitated by the need to minimize the overall silicon area and the critical path lengths. Test algorithms used to test reconfigured RAM's and scrambled address RAM's for the detection of physical neighborhood pattern sensitive faults have to consider that the physical and logical neighborhoods are different and that the address mapping of the reconfigured RAM is no longer available. In this paper, we present a test algorithm that detects static five-cell physical neighborhood pattern sensitive faults in reconfigured RAMs and RAMs with scrambled address lines. This algorithm is based on the widely used MSCAN and Marching test algorithms, and requires only O(N[log2N]) reads and writes to test an N-bit RAM array

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 9 )

Date of Publication:

Sep 1996

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