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Energy and performance efficiency of fetch unit is critical to processor design. Trace cache which stores dynamic instruction flow to form instruction trace can significantly improve performance efficiency by fetching multiple blocks from trace cache in a given cycle. Conventional trace cache (CTC) design suffers energy inefficiency because of its simultaneous access to both instruction cache and trace cache during each cycle but instructions from only one of them are used. The activation and access to the other results in energy waste. Many researchers have explored various approaches to avoid this problem to improve energy efficiency of trace cache, such as dynamic direction prediction based trace cache (DPTC). An alternative approach called advance direction directed trace cache (ADDTC) is proposed in this paper. By extending branch target buffer (BTB) with trace control information, whether trace cache hits or not can be predicted in branch prediction before the actual fetch. The fetch direction can be predicted and only the predicted one is accessed for energy saving. We evaluated the energy consumption and performance of ADDTC. Our experimental results show that ADDTC delivers fetch direction prediction accuracy as high as 88.4% on average. It reduces energy consumption by 39.9% with only 4.4% performance degradation compared to CTC. Our proposal also shows advantage of both energy and performance over DPTC. Energy consumption is reduced by 5.9% and performance is improved by 2.9% compared to DPTC.
Date of Conference: 22-25 Sept. 2009