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Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture

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3 Author(s)
Masuda, M. ; Adaptive Syst. Lab., Univ. of Aizu, Aizu-Wakamatsu, Japan ; Ben Abdallah, A. ; Canedo, A.

Queue processor offers an attractive option in the design of general purpose and applications specific systems. This paper presents software and hardware design issues for extracting high instruction level parallelism for the 32-bit queuecore processor. We propose code generation algorithm for the queuecore architecture. Compiling for the queuecore requires a new approach since the concept of registers disappears. The compiler extracts more parallelism than the optimizing compiler for a RISC machine over a set of various numerical benchmark programs. In addition, we are able to generate in average about 23% denser code than two embedded RISC processors.

Published in:

Parallel Processing Workshops, 2009. ICPPW '09. International Conference on

Date of Conference:

22-25 Sept. 2009