Solution Space Reduction of Simulated Evolution Algorithm for Solving Standard Cell Placement Problem

Simulated Evolution algorithm is versatile, efficient but very much time consuming. This paper shows that the reduction of trials in the allocation phase leads to the improvement of the performances of Simulated Evolution algorithm. In its application to the cell placement problem of VLSI chip, 90% reduction of the solution space in the allocation phase accelerates the total processing time, 4.6 ~ 7.7 times and improves the solution quality, 1.6 ~ 6.4% when compared with an exhaustive search of the solution space. This result is also useful for implementing Simulated Evolution algorithm on an FPGA.