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Runtime Adaptation in Reconfigurable System-on-Chips

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1 Author(s)
Ejnioui, A. ; Dept. of Inf. Technol., Univ. of South Florida Polytech., Lakeland, FL, USA

With the proliferation of portable devices, new multimedia-centric applications are continuously emerging on the consumer market. These applications are pushing computer architecture to its limit considering their demanding workloads. In addition, these workloads tend to vary significantly at run time as they are driven by a number of factors such as network conditions, application content, and user interactivity. Most current hardware and software approaches are unable to deliver executable codes and architectures to meet these requirements. There is a strong need for performance-driven adaptive techniques to accommodate these highly dynamic workloads. This paper shows the potential of these techniques in both software and hardware domains by reviewing early attempts in dynamic binary translation on the software side and FPGA-based reconfigurable architectures on the hardware side. It puts forward a preliminary vision for unifying runtime adaptive techniques in hardware and software to tackle the demands of these new applications. This vision will not be possible to realize unless the notorious reconfiguration bottleneck familiar in FPGAs is addressed. The paper concludes by pointing several future directions to explore in order to realize the full potential of runtime adaptation.

Published in:

Parallel Processing Workshops, 2009. ICPPW '09. International Conference on

Date of Conference:

22-25 Sept. 2009