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Synthesis of delay fault testability circuits

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1 Author(s)
S. Chakravarty ; Dept. of Comput. Sci., New York Univ., Buffalo, NY, USA

Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be “hazard free delay fault testable” is presented. In contrast to existing results that consider either “single path propagating hazard free robust tests” or “general robust tests” we consider “multiple path propagating hazard free robust tests” in our analysis

Published in:

IEEE Transactions on Computers  (Volume:45 ,  Issue: 8 )