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Augmented binary hypercube: a new architecture for processor management

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3 Author(s)
H. Lalgudi ; Zeitnet Inc., Santa Clara, CA, USA ; L. F. Akyildiz ; S. Yalamanchili

Augmented Binary Hypercube (AH) architecture consists of the binary hypercube processor nodes (PNs) and a hierarchy of management nodes (MNs). Several distributed algorithms maintain subcube information at the MNs to realize fault tolerant, fragmentation free processor allocation and load balancing. For efficient implementation of AH, we map MNs onto PNs, define and prove infeasibility of ideal mappings. We propose easily implementable nonoptimal mappings, having negligible overheads on performance. Extensive simulation studies and performance analysis conclude that these algorithms realize significantly better average job completion time and higher processor utilization, as compared to the best sequential allocation schemes and parallel implementation of Free List. AH algorithms can be tuned or adapt to the job and system characteristics, and resource management traffic

Published in:

IEEE Transactions on Computers  (Volume:45 ,  Issue: 8 )