A VLSI architecture of the trellis decoder block for the digital HDTV Grand Alliance system

This paper describes the design of a VLSI architecture for the trellis decoder block on a single-chip FEC (forward error correction) decoder supporting both the 8 VSB terrestrial broadcast mode and the 16 VSB high data-rate mode for cable proposed by the digital HDTV Grand Alliance (GA). The trellis decoder block consists of 12 trellis decoders, each of which is designed for the GA 8 VSB mode. In the proposed architecture, a unique branch metric unit is devised and employed for both the additive white Gaussian noise (AWGN) channel and the 1-D partial response channel. This makes the implementation complexity of the proposed trellis decoder much the same as that of a usual 8-state trellis decoder. The proposed trellis decoder works as the partial response trellis decoder when the NTSC rejection filter is activated to reduce the NTSC cochannel interference, while it works as the optimal trellis decoder when there is little or no NTSC interference.