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An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis

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2 Author(s)
Zuochang Ye ; Tsinghua Univ., Beijing, China ; Zhiping Yu

Statistical full-chip leakage analysis considering spatial correlation is highly expensive due to its O(N2) complexity for logic circuits with N gates. Although efforts have been made to reduce the cost at the loss of accuracy, existing methods are still unsuitable for large-scale problems. In this paper we resolve the problem by re-formulating the computation to one that can be done efficiently using a well-developed technique that has been widely used in fast EM simulation and machine learning areas. The resulting algorithm is provably of O(N) or O(N log N) complexity with well-defined and easily-controlled error bounds. Experiments show that using the proposed method it is feasible to handle million-gate circuits within only a few minutes on a regular desktop PC. The corresponding error is less than 0.5% compared to exhausted computation that takes more than 3 days. The proposed method is about 300× faster and 10× more accurate compared to existing grid-approximation method.

Published in:

Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on

Date of Conference:

2-5 Nov. 2009