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Video encoder architecture for MPEG2 real time encoding

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3 Author(s)
Geng-Lin Chen ; Comput. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan ; Jyh-Shin Pan ; Jia-Lung Wang

A video encoder architecture for encoding digital video signals based on the MPEG2 video standard up to the slice level is described. A function specific architecture is implemented to increase the coding efficiency and reduce the silicon area for real time encoding. A hierarchical control concept is adopted and a three-stage pipeline encoding method is used in the macroblock coding to increase the flexibility of the encoding flow and reduce the design effort. Most of the computing power for the MPEG2 encoding algorithm is utilized in motion estimation, so a separate motion estimation module is used as a coprocessor. The motion estimation algorithm adopted is a full search with the search window in the range between +47 and -48 pels in the horizontal direction and between +15 and -16 pels in the vertical direction. Simulations on several video sequences with different target bit rates are evaluated. The results show that our implementation can achieve a video quality comparable to other off-line software simulation programs using exhaustive searches

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Consumer Electronics, IEEE Transactions on  (Volume:42 ,  Issue: 3 )