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Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test

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4 Author(s)
Chen-I Chung ; Dept. of Electron. Eng., Feng-Chia Univ., Taichung, Taiwan ; Jyun-Sian Jhou ; Ching-Hwa Cheng ; Sih-Yan Li

The self wide-range (26%~76%), fine-scale (34 ps) duty cycle adjustment technique with high-precision (28 ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.

Published in:

2009 Asian Test Symposium

Date of Conference:

23-26 Nov. 2009