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On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification

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3 Author(s)
Po-Yuan Chen ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Cheng-Wen Wu ; Ding-Ming Kwai

We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of the inherent capacitive characteristics, we can detect the faulty TSVs with little area overhead for the circuit under test.

Published in:

Asian Test Symposium, 2009. ATS '09.

Date of Conference:

23-26 Nov. 2009