Referenced Items are not available for this document.
We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of the inherent capacitive characteristics, we can detect the faulty TSVs with little area overhead for the circuit under test.
Published in:
Asian Test Symposium, 2009. ATS '09.
Date of Conference: 23-26 Nov. 2009
- Page(s):
- 450 - 455
- ISSN :
- 1081-7735
- Print ISBN:
- 978-0-7695-3864-8
- INSPEC Accession Number:
- 11052868
- Conference Location :
- Taichung
- Digital Object Identifier :
- 10.1109/ATS.2009.42
- Product Type:
- Conference Publications
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