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A 212 MPixels/s 4096 \times 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications

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9 Author(s)
Li-Fu Ding ; Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Wei-Yin Chen ; Pei-Kuei Tsung ; Tzu-Der Chuang
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Multiview video coding (MVC) plays an important role in a 3-D video system. In addition, the resolution of HDTV is increasing to present more vivid perception for users. To realize real-time processing of dozens of TOPS, VLSI solution is necessary. However, ultra high computational complexity, a large amount of external memory bandwidth and on-chip SRAM size, and complex MVC prediction structures are three main design challenges of implementation of MVC hardware architecture. In this paper, an MVC single-chip encoder is proposed for H.264/AVC Multiview High Profile and High Profile for 3-D and quad full high definition (QFHD) TV applications, respectively. The 4096 × 2160 p multiview video encoder chip is implemented on a 11.46 mm2 die with 90 nm CMOS technology. An eight-stage macroblock pipelined architecture with proposed system scheduling and cache-based prediction core supports real-time processing from one-view 4096 × 2160 p to seven-view 720 p videos. The 212 Mpixels/s throughput is 3.4 to 7.7 times higher than previous work. The 407 Mpixels/W power efficiency is achieved, and 94% on-chip SRAM size and 79% external memory bandwidth are saved by the proposed techniques.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:45 ,  Issue: 1 )