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A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

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14 Author(s)
Iwata, K. ; Renesas Technol. Corp., Kodaira, Japan ; Irita, T. ; Mochizuki, S. ; Ueda, H.
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A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a 6.4 × 6.5 mm2 die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 1 )

Date of Publication:

Jan. 2010

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