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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

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21 Author(s)
Uksong Kang ; Samsung Electron., Hwasung, South Korea ; Hoe-Ju Chung ; Seongmoo Heo ; Duk-Ha Park
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An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.

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Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 1 )