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A novel circuit topology of the quadrature voltage-controlled oscillator (QVCO) is presented in this paper for low-voltage and low-power applications. With the antiphase coupling provided by the MOSFETs in a passive mode, quadrature output phases can be generated at minimum power consumption while maintaining desirable circuit performance in terms of phase error and phase noise. Based on the proposed QVCO circuit, an integer-N phase-locked loop (PLL) is implemented in a standard 0.18-??m CMOS process. As the building blocks are optimized for low-voltage and low-power operations, the fabricated 2.4-GHz PLL consumes a dc power of 14.4 mW from a 0.6-V supply. By applying a reference frequency of 20 MHz, the measured spur rejection and phase noise at 1-MHz offset are 39.83 dB and -104.69 dBc/Hz, respectively. From the output waveforms, the phase error of the quadrature output is 2.21?? .