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This paper discusses scheduling characteristics unique in stacked chips [including multichip package (MCP) and multidie package (MDP)] production process such as reentrant work flow and synchronization constraint. It also proposes a modeling and analytical framework for stacked chips assembly operations, which is based on the formal framework of generalized stochastic Petri net. This approach allows the seamless integration of the logical and timed dynamics of stacked chip assembly operations in a single representation. Furthermore, the proposed framework supports the analytical representation of the stacked chips scheduling problem as a mathematical programming formulation, which can be effectively solved to optimality through enumerative techniques. The framework presentation and its capabilities are elucidated by detailed application on a small system configuration for MCP.