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A 1.35GHz all-digital fractional-N PLL with adaptive loop gain controller and fractional divider

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5 Author(s)
Deok-Soo Kim ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Heesoo Song ; Taeho Kim ; Suhwan Kim
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A 1.35 GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang-bang phase-frequency detector (BBPFD). The fractional divider partially compensates for the input phase error which is caused by the fractional-N frequency synthesis operation. A prototype ADPLL using a BBPFD with a dead zone free retimer, an ALGC, and a fractional divider is fabricated in 0.13 ¿m CMOS. The core occupies 0.19 mm2 and consumes 13.7 mW from a 1.2 V supply. The measured RMS jitter was 4.17 ps at a 1.35 GHz clock output.

Published in:

Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian

Date of Conference:

16-18 Nov. 2009