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A 1.35 GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang-bang phase-frequency detector (BBPFD). The fractional divider partially compensates for the input phase error which is caused by the fractional-N frequency synthesis operation. A prototype ADPLL using a BBPFD with a dead zone free retimer, an ALGC, and a fractional divider is fabricated in 0.13 Â¿m CMOS. The core occupies 0.19 mm2 and consumes 13.7 mW from a 1.2 V supply. The measured RMS jitter was 4.17 ps at a 1.35 GHz clock output.
Date of Conference: 16-18 Nov. 2009