Close category search window
 

A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Wen-Yi Pang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chao-Shiun Wang ; You-Kuang Chang ; Nai-Kuan Chou
more authors

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. Splitting comparator and energy saving capacitor array are proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 69% compared to a conventional switching method. The measured signal-to-noise-and-distortion ratios of the ADC is 58.4 dB at 500 KS/s sampling rate with an ultra-low power consumption of 42-¿W from a 1-V supply voltage. The ADC is fabricated in a 0.18-¿m CMOS technology.

Published in:
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian

Date of Conference: 16-18 Nov. 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.