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A low latency transceiver macro with robust design technique for processor interface

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5 Author(s)
Zhang Feng ; Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China ; Yang Yi ; Yang Zongren ; Chiang, P.
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This paper describes a 65 nm 16-bit parallel transceiver IP macro, whose bandwidth is 4.8 GByte/s with 5 pf load including the HBM 2000v ESD protection. Equalizers and CDR modules, CRC checkers and 8b/10b encoders are not added in the design for reducing the latency and the whole latency is 7 ns without cables. Since the transceiver has many robust features including a PVT independent PLL with calibrations, the low skew differential clock tree, a stable current mode driver with common mode feedback. The transceiver can tolerance 20% power supply variations and work properly at different process corners and the extreme temperatures. The transceiver can be applied for the interface of sub-100 nm high performance processors which require low latency and high stability. The transceiver shows a BER less than 10-15 at 3 Gb/s/pin.

Published in:

Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian

Date of Conference:

16-18 Nov. 2009