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A 329mW 600M-Pixels/s dual-stream coarse-grained reconfigurable image stream processor is implemented in TSMC 0.13Â¿m CMOS technology with a core size of 4.84mm2. The reconfigurable pipelined processing element array architecture makes a good balance between computing performance and flexibility with only 10Kb on-chip memory. Moreover, a new dual-stream architecture is proposed to improve the flexibility and hardware efficiency by processing two independent image streams with two-layer context switching, and an isolation technique is also proposed to improve the power consumption. Implementation results show that it achieves 1.52 times power efficiency than previous works and can meet the requirements of high-definition video camcorders and digital still cameras.