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A high-frame-rate dense motion vector field generation processor employing an efficient data manipulation scheme has been developed. The computation result of detecting a motion vector (MV) at each pixel location is reused in the adjacent location. As a result, the size of a best-match searching circuitry for MV detection has been reduced to 1/10 of that without data reuse. This allows us to implement two MV calculation units on a chip without area penalty, enabling dual MV generation at every clock cycle except for the initial period of overhead processing. As a result, the frame rate has been increased by 23% as compared to the previous architecture, while the total number of transistors has been reduced by 41%. A prototype chip was designed and fabricated in a 0.18-Â¿m 5-metal CMOS technology. It was experimentally demonstrated that the chip can generate motion vectors from all pixel sites of 256Ã256-size motion images at a frame rate of 1060 frames/sec with a clock frequency of 100 MHz.