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A novel dual processing architecture for implementation of motion estimation unit of H.264 AVC on FPGA

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2 Author(s)
Vikram Arkalgud Chandrasetty ; IEEE Graduate Student Member, Bangalore, India ; Shridhar R Laddha

In this paper, a Blot Search or One Step Search Motion Estimation algorithm is chosen for hardware modeling, based on the performance results obtained from simulations of a software reference model. The architecture of the model is designed to maximize the throughput of the system. The current frame and reference frame data are pipelined to the Motion Compensation block consisting of dual Residual Energy computation and comparison units. The prototype model is tested on Xilinx Vertex 4 FPGA. The design can process each macro block of N pixels in N + 2 clock cycles at a maximum operating frequency of 116 MHz. At this frequency, the designed Motion Estimation unit can process an HDTV resolution frame of 1920 × 1080 pixels at 55 frames per second with an estimated total power consumption of 543 mW.

Published in:

Industrial Electronics & Applications, 2009. ISIEA 2009. IEEE Symposium on  (Volume:1 )

Date of Conference:

4-6 Oct. 2009