Skip to Main Content
Existing silicon validation techniques only address test data capture issues. They all assume the existence of live traffic in the system. Unfortunately, this is not always the case in real life. This paper proposes a novel design methodology for silicon validation and system integration. It uses built-in functional tests to simulate live traffic at full speed when a real one is not available at the arrival of the first silicon. The proposed methodology provides a platform upon which many silicon validation and system integration tasks can be performed before a real traffic is ready. It can also be used to cover logic corner cases that may not be easily achievable in real life. The proposed methodology has been proven effective on time-to-market and quality of verification with multiple complex system-on-chip designs.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 4 )
Date of Publication: April 2011