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Tolerance of performance degrading faults for effective yield improvement

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5 Author(s)
Tong-Yu Hsieh ; Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan ; Melvin A. Breuer ; Murali Annavaram ; Sandeep K. Gupta
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To provide a new avenue for improving yield for nano-scale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.

Published in:

2009 International Test Conference

Date of Conference:

1-6 Nov. 2009