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This 32 b superscalar processor, having 18 mW/MHz projected power consumption at 66 MHz, is designed for desktop companions and high-end embedded multimedia applications with graphics-intensive requirements such as high-performance video games. This processor, the latest member of the PowerPC microprocessor family, can also be used in other low-power computing applications. The processor is fabricated in a 3.3 V, 0.5 m, 4-level metal CMOS resulting in 1 M transistors in a 7.07/spl times/7.07 mm/sup 2/ chip. Dual 4 kB instruction and data caches coupled to a high-performance 64 b multiplexed bus and separate execution units (float, integer, branch, and load-store) result in 2 instructions per clock cycle peak rate. Low-power design includes dynamically-powered-down execution units. Standby power is <2 mW. CPU to bus clock ratios of 2/spl times/ and 3/spl times/ allow control of system power while maintaining processor performance.
Date of Conference: 15-17 Feb. 1995