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The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is a field programmable gate array (FPGA) with heterogeneous mixture of device primitives. In this study, the authors present scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. The authors present the results of a rigorous analysis of the methodology on multiple test cases. Post place and route results are compared against published techniques and show an area savings and execution time savings of 46% each.