Skip to Main Content
This study presents a method for implementing a circuit in a field programmable gate array (FPGA) that protects the circuit from the effects of single-event upsets (SEUs). When routing nodes within the circuit using the interconnect lines of the FPGA, two routed nodes are separated from each other by at least two programmable interconnect points (PIPs). Therefore if an SEU causes a PIP to become inadvertently enabled, the affected node is coupled to an unused interconnect line, instead of to another node within the circuit. When a triple-modular redundancy (TMR) circuit is implemented using the proposed scheme, signals in one module are separated from signals in another module by at least two PIPS to prevent the short effects of SEUs. However, signals within the same module can be separated by only one PIP, because the TMR structure can compensate for errors within a single module.